UVM tutorial for beginners- Getting Started

Hello and Welcome to the UVM tutorial for beginners. In this tutorial, you will learn about several key concepts of UVM that will enable you to write a full blown verification testbench in UVM. The tutorial has been written with an assumption that the reader has knowledge of System Verilog and Object Oriented Programming.

For system verilog, please refer to our partner website www.asic-world.com and I will write a separate blog soon on Object Oriented Programming concepts used in UVM like Classes, Objects, Virtual function, Polymorphism ( – Stay tuned for that ! ).

UVM Tutorial for beginners

In this blog we will go through:

  1. Introduction
  2. Bird’s eye view – UVM Test
  3. Concept of UVM factory and UVM configuration database.
  4. Transactions and Sequences in UVM
  5. UVM Environment
  6. Sequencers and drivers
  7. Monitors and agents
  8. Scoreboards
  9. Coverage Collectors
  10. Tests, Complex sequences and top modules
  11. Phases in UVM
  12. UVM Register layer overview.
  13. Analysis Ports and FIFOs.
  14. Virtual Sequencer.
  15. UVM macros: uvm_do, uvm_object_utils.

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Please note we will continue to revisit these blogs and make corrections to spelling and grammatical mistakes from time to time. Also, we will continue to fix any coding issues that we may come across. If you would like to report any coding issues or grammatical mistakes, please write to us at contact@asictronix.com with Subject “Suggestions for UVM blog”. Reporting of errors will be appreciated and we will fix the issues as soon as we can.

Thank you for visiting my page – “UVM tutorial for beginners” and I look forward to writing more blogs. You can now begin your UVM journey and enjoy learning it. Have fun !

NEXT –> Introduction

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