Design Verification

Design verification is a critical part of project
development and plays an important role in maintaining
incident-free operations.We have the one of the strongest team in ASICtronix. Our team can execute verification from scratch of complex SoC’s and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage. We also provide silicon proven VIP for latest IP’s and provide source code and aftersales support to our customers.

• Advanced IP & SoC Verification
• SV-UVM Based Constrained – Random Verification
• Verification Plan, Environment, Test Bench Development
• Low Power Verification
• Gate Level simulation
• Assertion based Formal Verification
• VIP Development and Integration
• Palladium, Zebu & Veloce based Validation Silicon validation

We do a comprehensive design verification & testing to catch all bugs in pre-silicon phase, achieving 100% Functional & Code Coverage. Our team has experience in building modular and reusable verification environment.

Process, Methodologies, Tools

• Mixed language (Verilog, VHDL, SystemVerilog, SystemC)
• Uniform language and methodology (UVM)

• VCS, IUS, Questa, MBD
• UVM, OVM, VMM, eRM