Developing high quality RTL is challenging because the chip needs to be low on area and power consumption and at the same time provide adequate performance. To overcome this, we leverage dozens of years’ experience of our team and follow stringent design checklist. To summarize we have expertise in the below ASIC design skill:
ASIC Design
- Micro-architecture chip design
- RTL design
- Functional verification
- SoC integration
- ASIC IP development
FPGA Design – Verification
- Test bench generation
- Functional simulation and assertions
- Code and functional coverage
- Post-synthesis simulation
- Script creation (tcl, perl, etc…)
FPGA Design – Tools Supported
- ModelSim (VHDL & Verilog)
- Altera Quartus
- Xilinx ISE and Vivado
- MicroSemi Libero
FPGA/EPLD Design more…
- VHDL, Verilog, State Diagram
- FPGA Place & Route
- Timing optimization
- ASIC and FPGA Verification
- Triad Semi structured ASICs
Altera FPGA Design Expertise
- Cyclone V SoC design
- H.264 video compression
- DVI 1080p30 video input
- Linux UDP Real Time video streaming over LAN
- 1.5GHz 2 Channel Digital Storage Scope (DSO)
- 8 Channel Arbitrary Waveform Generator
- 3 Channel Video Mux and Display Controller
- 4 Channel 8VSB studio HD Tuner
Xilinx FPGA Design Expertise
- High Speed w/ both ARM cores
- Networked DVR
- SATA
- Utilizes DDR III memory
- 1G Ethernet
- USB
- Input 6 NTSC channels
- On screen display
- Load balancing between ARMs
- Linux drivers & applications